QNX PTP Pulse-Per-Second Output on Intel i210: Implementation and Validation

1. Background and Motivation

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A requirement for a custom QNX network driver was to support pulse-per-second (PPS) signal output, similar to the Linux PTP_PEROUT_REQUEST ioctl. PPS is commonly used for precise time synchronization across distributed systems.

To achieve this, a custom IOCTL interface and a utility tool were implemented to enable or disable PPS output from the network interface.

2. Test Platform and Hardware Selection

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The implementation was validated on:

• Platform: Generic x86_64 system with QNX 7 BSP
• Default NIC: Intel i219 (no hardware PTP support)
• Test NIC: Intel i210 PCIe card (with full PTP capability)

The Intel i210 was selected because it provides hardware timestamping and programmable GPIO (SDP pins), which are essential for PPS output.

3. Hardware Mechanism: PPS via SDP Pins

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The Intel i210 supports time-triggered outputs through its SDP (Software Defined Pins).

Key Registers

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• TRGTTIML/H: Target time registers
• SYSTIML/H: System PTP time
• TSSDP: SDP configuration
• TSAUXC: Auxiliary control

PPS Generation Principle

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1. Configure a programmable clock synchronized to the PTP clock
2. Set clock period to 500 ms → produces a 1 Hz square wave
3. Align output with whole-second boundaries using target time registers
4. Automatically toggle output when system time matches target time

This method matches the approach used in the Linux igb/e1000 driver.

4. Driver Implementation

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4.1 IOCTL Extension

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Support for PPS control was added:

case PTP_ENABLE_PPS: 
    e1000_ptp_pps_enable(i82544); 
    return EOK;

case PTP_DISABLE_PPS: 
    e1000_ptp_pps_disable(i82544); 
    return EOK;

4.2 PPS Enable Logic

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Key steps:

1. Configure SDP0 as output
2. Route programmable clock (FREQ0) to SDP0
3. Disable existing clock
4. Set frequency (500 ms half-cycle)
5. Align start time with PTP clock
6. Enable clock output

uint32_t half_cycle = 500000000U;  /* 500 ms */
E1000_WRITE_REG(hw, E1000_FREQOUT0, half_cycle);

The clock starts slightly in the future (e.g., +2 seconds) to ensure proper synchronization.

4.3 PPS Disable Logic

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Disabling involves:

• Stopping the clock
• Removing signal routing from SDP pin

5. BSP Integration

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Since the default BSP lacked driver source:

• Modified driver was built from another BSP (e.g., Gordon Ridge)
• Integrated into system via:

devnp-e1000-pps.so=.../devnp-e1000.so

6. Runtime Configuration

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6.1 Replace Default Driver

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ifconfig wm1 destroy
io-pkt-v6-hc -i3 -ptcpip prefix=/sock3
mount -Tio-pkt3 -o vid=0x8086,did=0x1533,ptp devnp-e1000-pps.so
SOCK=/sock3 ifconfig wm0 192.168.204.8

6.2 Start PTP Daemon

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SOCK=/sock3 ptpd -g -C -b wm0 -L

6.3 Enable PPS Output

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SOCK=/sock3 pps-ctl -d wm0 -p 1

7. Signal Validation

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Setup

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• PPS output from QNX system (slave)
• PPS reference from Linux system (master)
• Measured using dual-channel oscilloscope

Results

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• PPS signal successfully generated on SDP0
• Stable synchronization achieved after convergence
• Observed jitter: ~1.4 microseconds

8. Key Takeaways

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• Intel i210 provides robust hardware support for PTP and PPS
• QNX drivers can be extended with custom IOCTL interfaces for advanced timing features
• Synchronizing programmable clock outputs with PTP time enables precise PPS generation
• Multi-stack networking in QNX is essential when replacing default drivers
• Achieved microsecond-level accuracy suitable for many industrial and telecom applications

9. Conclusion

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This implementation demonstrates a practical method for adding hardware-synchronized PPS output to a QNX-based system using the Intel i210 NIC. By leveraging existing PTP hardware features and extending the driver with minimal modifications, it is possible to achieve reliable, high-precision timing output comparable to Linux-based implementations.

This approach is especially valuable in systems requiring time synchronization, distributed coordination, or precision measurement, such as telecommunications, industrial control, and embedded networking.